Fan-out wafer level packaging is becoming more popular in recent years, due to low cost, good reliability and ease of multi-chips integration. Fan-out packages are widely adopted in mobile applications due to the low package profile because such packages do not involve the use of a ball grid array (BGA) substrate. First generation fan-out wafer level packages involve laterally connecting embedded chips using re-distribution layer (RDL) layers on the surrounding mold compound. Second generation and third generation of fan-out wafer level packages include vertical interconnects in the mold area for package on package (PoP) stacking application.
For mobile applications, the desirable package height should be lower than 1 mm. However, conventional PoP stacks are very high due to BGA substrate and thick solder balls used to connect top and bottom package. Fan-out wafer level packages have been effective in reducing the package height, but considerable efforts are required to further reduce the stacked package height.